Dottorato in TECNOLOGIE DELL'INFORMAZIONE E DELLE COMUNICAZIONI (ICT)

Titolo della tesi: Shielding the Future: Hardware Security Leveraging Physical Unclonable Functions and True Random Number Generators

This Ph.D. thesis presents an in-depth investigation into the design, implementation, and performance optimization of Physical Unclonable Functions (PUFs), True Random Number Generators (TRNGs), and reconfigurable entropy sources, with a particular focus on their applicability to both Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs). The research is driven by the growing demand for secure and unpredictable entropy sources in various applications, including cryptographic systems and hardware security. With respect to the design of PUF on ASIC, the primary emphasis has been on achieving energy efficiency while minimizing bit error rates and response instability in PUFs. The research delves into novel design techniques to optimize the performance of PUFs, ensuring their reliability and suitability for resource-constrained applications. Additionally, extensive validation under varying voltage and temperature conditions ensures robustness and practical applicability. On the other hand, for what concern the design of PUF on FPGA, the objective has been to strike a balance between resource utilization, reliability, and uniqueness. This work explores strategies to achieve the best possible compromise among these critical parameters, contributing to the development of PUFs that are well-suited for deployment on reconfigurable hardware platforms. The research on TRNGs begins with a focus on FPGA design, specifically addressing resource-constrained architectures. Subsequently, novel TRNG architectures are proposed, enhancing throughput while minimizing resource consumption and maintaining high entropy levels. These contributions aim to cater to the diverse requirements of applications that demand high-quality random number generation. With respect to the design and development of reconfigurable entropy sources, the aim of this research is to find the optimal tradeoff between PUFs and TRNGs, recognizing their distinct performance and use cases. The investigation leads to the development of hybrid entropy sources that capitalize on the strengths of both PUFs and TRNGs, ensuring flexibility in tailoring entropy generation to specific application needs. To facilitate the comparison of various architecture designs, this thesis introduces comprehensive figures of merit for both PUFs and TRNGs. These metrics offer a structured framework for the assessment and comparison of various designs, enabling individuals to make conscious decisions regarding the selection and incorporation of entropy sources into their systems. The findings of this research not only contribute to the advancement of secure hardware design but also provide valuable insights into the development of efficient and reliable entropy sources, benefiting a wide range of applications. Measured results on ASIC and FPGA, alongside the proposed figures of merit, offer a comprehensive perspective on the performance and suitability of the designed entropy sources.