Phd in INFORMATION AND COMMUNICATION TECHNOLOGY (ICT)

Thesis title: Enhancing Fault Tolerance in Interleaved Multi-Threading RISC-V Processors: A Microarchitectural Approach

In the rapidly advancing technological era, the likelihood of errors arising from voltage glitches caused by ionizing particles in digital chips rises as the minimum feature size and voltage margins decrease, compounded by increased statistical process variations [6][67][14]. The capacity to address circuit faults to preserve functional safety, ensuring the reliability and resilience of critical applications, commonly called fault tolerance (FT), has conventionally been associated with aerospace, avionics, and military applications where uninterrupted functionality is imperative for mission success, safety, and operational efficiency. However, it has been recognized as playing a central role in ground-level industrial processes, crucial for economic efficiency, safety of workers and intelligent transportation systems [15], which increasingly rely on digital integrated circuits. This work fits the vast scenario of microprocessor devices for fault tolerance applications, proposing an Interleave Multi-Threading (IMT) set of structures with a detailed architectural analysis and new fault tolerance techniques correlated with interesting performance, overhead and power consumption results.