Phd in INFORMATION AND COMMUNICATION TECHNOLOGY (ICT)

Thesis title: Design and development of fault-tolerant architectures for space-qualified RISC-V processors.

The first decades of the twenty-first century marked the beginning of a new space race. Driven by new private industry giants like SpaceX and BlueOrigin introducing new philosophies of reusable space launchers, this space renaissance has reduced the cost of launch to unprecedented levels, allowing many new realities in the university and industrial fields to enter this rapidly expanding sector. However, for many small companies, the cost of developing a satellite plus launch still remains too high, also due to the high costs of components dedicated to the sector. The usage of Commercial Off-the-Shelf (COTS) components as well as an open-source Instruction Set Architecture (ISA) allows a reduction in cost due to the low volume demand for aerospace applications. Furthermore, the possibility of soft-cores implemented in FPGAs opens the way to additional improvements for adapting the system to the effects of harsh environments. Since the electronic devices that operate in the harsh space environment require a high grade of reliability, and COTS components are not intrinsically protected at the circuit level, a fault-tolerant architecture is required to cope with the severe environment requirements as well as with resource availability. In this study, we demonstrate the reliability of new fault-tolerant soft-core architectures that can be used in small low-cost satellites with low-end FPGA. We start from the well-known classic fault-tolerant techniques applied in pervasive ways to an already developed design and use it as a reference. From that design, we develop new architectures that decrease the application of the fault-tolerant techniques but increase performance with less area resources used, and support of dedicated peripherals designed to preserve the reliability. The fault reliability of designs has been tested through two different fault injection RTL testbench. The first one developed is script-based and reports the ability of an architecture to complete the test performed and in how much time during a fault injection. The second one is a UVM testbench that can analyze in detail the behavior of the architecture during a fault injection, reporting the error probability and the sensitivity of the architecture to a fault. The microprocessors and System-on-Chip (SoC) presented are a part of a family of processing cores and processors called Klessydra. The Klessydra microprocessors were written such that they have a pinout that is 100 percent identical to Riscy cores from PULPino SoC. The subset of the Klessydra cores presented in this thesis belongs to the group called the Klessydra-F, fault-tolerant core versions derived from the Klessydra-T group, where the letter ‘T’ indicates that the cores are multithreaded. Klessydra-F subset has many implementations and the one developed throughout this thesis is Klessydra-F03x-mini or F03x-mini. The new family of SoC presented in this thesis is called the HydraSoC and is derived from PULPino SoC. The HydraSoC has two main implementations used throughout this thesis which are HydraSoC v1 and HydraHCA. In order to test and study the new fault-tolerant techniques in space, an orbital test laboratory called Klessydra Orbital Space Lab or KOL has been developed. This Lab is the payload launched on a space satellite launched within a European Space Agency initiative. The satellite architecture is then composed by the Microcontroller Unit MCU control and communication board and a COTS FPGA board that embedded the KOL and it has been designed to be programmed via “Over-the-Air” (OTA) update to test different architectures in the real environment.