Thesis title: High-speed low-voltage and ultra low-voltage SAR ADC
In this thesis work several techniques to optimize SAR (Successive Approximation
Register) ADC (Analog-to-Digital Converter) performances have been investigated.
The thesis work has been focused on two vertical topic: high speed SAR ADC and
LV (Low-Voltage) and ULV (Ultra-Low-Voltage) ADC. The structure of the work is
based on the research activity carried out in the three years of the PhD. The first
activity that was carried out is the design of an HS (High-Speed) SAR ADC that
has been realized in foundry. Subsequently, much of the activity has been focused
on the development of innovative technique and topology aimed at the optimization
of LV and ULV dynamic comparator, then a complete ULV ADC has been realized
with one of this comparator, finally a wide band LPF (Low-Pass Filter) for analog
front-end of HS ADC has been realized. The document is structured as follow:
The first chapter introduces the work describing the context and the state of the
art of the ADC in general and of the SAR ADC in particular. The chapter reports
the aims of this thesis and describes the content of all the chapters.
The second chapter contains a theoretical introduction on the ADC in general,
reporting the working principles, applications, main characteristics and definitions.
The chapter deepens the analysis of the SAR ADC, describing the building blocks
and in particular the dynamic comparators.
In the third chapter of the thesis, a 166 MS/s 10 bit VDD = 1 V fully differential
SAR ADC has been designed and tested. The design has been sent to the foundry
to be realized within an integrated circuit. The ADC shows good performance in
terms of accuracy despite its FOM (Figure Of Merit) is not competitive. The design
of this SAR ADC allowed to validate an innovative switching algoirthm used to
optimize conventional Strongarm comparator performances.
The fourth chapter presents a a 6.67 MS/s 8 bit VDD = 0.4 V fully differential
ULV SAR ADC. The chapter describes the ADC architectures and every building
blocks, with particular emphasis on the dynamic comparator that is the most
innovative element of the ADC. Finally reports the post-layout simulation results
both for the comparator and the ADC, highlighting the competitive performances
in terms of speed at a supply voltage as low as 0.4 V.
The fifth chapter is dedicated to a survey of LV and ULV comparators. A
series of innovative topology and technique to optimize the speed-consumption
trade-off at Low and Ultra low supply voltage are presented in this chapter. detailed
theoretical models on the delay behaviour of the Strongarm based ULV comparator
are presented in this chapter. Particular attention was reserved to the study of the
comparator transistors operating in subthreshold region and to the study of the
CPB (Charge Pump-Based) dynamic biasing. All the presented comparators have
been simulated (almost all with post-layout simulations) and the performances that
have been evaluated are competitive with the state of the art.
In the sixth chapter of the thesis a 17 GHz inductorless LPF has been designed
and tested, the LPF is an innovative topology based on a modification of conventional
Sallen-key topology. This topology involves the internal poles of the amplifier in
order to enlarge the bandiwdth of the filter. The filter shows very competitive
performance in terms of band, noise and linearity.