Thesis title: Real-Time Multi-Channel Neural Signal Processing Architectures Exploiting an Ultra-Low-Complexity Algorithm-Hardware Co-Design Approach
This dissertation investigates hardware-efficient strategies for real-time, multi-channel neural signal processing architectures, through an algorithm–hardware co-design approach. The proposed solutions are applied to two complementary domains, namely automated epileptic seizure detection and neural spike sorting, showing that the synergy between algorithmic optimization and hardware-aware design is key to achieving efficient and scalable neural interfaces. The first part of this research presents the development of a real-time, on-chip spike sorting system for neural signals acquired through implantable microelectrode arrays. The design implements a digital processing chain capable of classifying neural spikes according to their source neurons, enabling significant data reduction for wireless transmission while respecting stringent power and area constraints of implantable devices. The proposed architecture is coded in custom VHDL and hardware-oriented Simulink model. Synthesis was then performed on both ASIC and FPGA platforms to assess the resource allocations of the proposed implementations. Both single-channel and multi-channel variants of the spike sorting architecture have been developed. For the ASIC implementation, the design of the single-channel proposal was synthesized on 130 nm and 28 nm FD-SOI CMOS processes, achieving area and power consumption of 0.2659 mm²/ch and 7.16 µW/ch for the 130 nm process, and 0.0168 mm²/ch and 0.47 µW/ch for the 28 nm process, respectively. FPGA implementation of the proposed multi-channel TDM-based acquisition and detection system demonstrates its extremely low resource requirements. The architecture achieves minimal utilization of logic resources, with only 94 LUTs (0.017%), 140 flip-flops (0.013%), and 2 DSP slices (0.079%) employed. The second part of this work addresses the FPGA deployment of a threshold-based, real-time, multi-channel automatic seizure detection algorithm, designed for low-complexity hardware implementations. The algorithm relies on two computationally simple time-domain features, based on power and amplitude variations, enabling accurate and timely detection by rapidly adapting to fluctuations in neural activity. System thresholds are optimized through an offline calibration process that exploits statistical analyses of patient-specific inter-ictal and ictal periods, while a multi-channel decision-making strategy enhances robustness against false alarms. The proposed algorithm is tested on multiple datasets to assess its adaptability to different recording conditions, achieving roughly 98% accuracy and over 98% sensitivity on both the EEG CHB-MIT dataset and the iEEG SWEC-ETHZ dataset, with average latencies of 3.37 seconds and 7.84 seconds, respectively. These results are comparable to, and in some cases outperform, several published machine-learning-based approaches. FPGA synthesis results highlight the minimal and scalable resource requirements of the proposed architecture, achieved through time-division multiplexing (TDM) of both filtering and feature extraction, making it suitable for real-time, resource-constrained hardware deployment. The proposed design achieves the lowest usage of hardware resources compared to other state-of-the-art works. In particular, it requires only 3 DSP blocks, demonstrating an efficient mapping of the algorithm to hardware. Importantly, DSP utilization remains constant regardless of the number of channels, as they are shared through the TDM scheme, unlike conventional approaches where DSP demand scales with channel count. The outcomes of both applications highlight the efficiency and scalability of the proposed hardware architectures, underscoring their suitability for resource-constrained and implantable systems.