Dottorato in TECNOLOGIE DELL'INFORMAZIONE E DELLE COMUNICAZIONI (ICT)

Titolo della tesi: Cutting-Edge Switching Approaches in Brain-Implanted Neural Devices: Advancing Neurotechnology

In recent years, neuroscience research has undergone considerable interest in both academic and industrial environments, driven by the development of innovative neurotechnologies capable of monitoring complex brain functions with remarkable spatial and temporal resolution. These advancements enable the diagnosis of neurodegenerative diseases and the delivery of targeted therapies with increasingly sophisticated and miniaturized systems, minimizing disruption to the routines of patients. However, the demand for devices with high-resolution for monitoring brain functionality requires challenging designs with substantial hardware resources, resulting in bulky systems for chronic implants. This has prompted more and more neuroelectronic designers to develop cutting-edge neural recording systems that offer high integration and low power consumption. An important limitation for integrating such systems, is due to the bandwidth of neural signals, ranging from 0.1 Hz to 10 kHz and to their DC input offset. The processing of these signals and the rejection of this offset, requires filters with large time constants. In CMOS technology, conventional filter implementation demands significant silicon area, making the integration of such systems increasingly challenging. To address these issues, a novel approach is presented by the Switched-Resistor technique, which overcomes these issues by enabling the implementation of large time constants with enhanced integration while better fulfilling the different application requirements. Nowadays, the design of a system based on Switched-Resistors requires a huge amount of effort owing to the lack of a detailed model that highlights the performance degradation due to parasitic phenomena. In this dissertation, two detailed models of the Switched-Resistor technique involving both operating and noise behaviour have been developed. The proposed models have been validated by means of simulation through PSS, PAC, and PNOISE analysis within the Cadence VirtuosoTM environment, referring to a commercial 130nm CMOS technology. In the first model, an in-depth analysis of the Switched-Resistor technique has been carried out, taking into account the parasitic capacitances of the integrated poly resistors and the non-ideal resistance of the CMOS switches. The model allows to accurately predict the value of the equivalent resistance even for values of the duty cycle as low as 0.0001%, a range where the conventional model already proposed fails. Simulation results have shown an average and maximum error of the model lower than 0.53% and 5.15% respectively. As a further validation, a first-order active low-pass filter has been implemented, showing average and maximum errors in the estimation of the cutoff frequency lower than 3.6% and 7%, respectively. The second model entails the characterization of the cyclostationary noise of the Switched-Resistor. Since Switched-Resistor circuits can be considered as linear periodically time variant (LPTV) systems with sampled outputs, the theory of adjoint (inter-reciprocal) network has been exploited to develop a detailed noise model, by gaining insight into the different noise sources and transfer functions involved. Simulation results performed against the main device parameters have shown great model accuracy, exhibiting an average relative error across the whole duty cycle range of 2.3%. The validation activity has confirmed the good accuracy of the proposed noise model and provided some useful design guidelines to optimize the noise performance of S-R circuits. Several circuits exploiting the switched-resistor approach for neural recording applications are proposed in this thesis. For the first time in the literature, biquadratic filters based on different implementations of the Switched-Resistor have been proposed. First, it has been proposed a straightforward implementation based on the grounded Switched-Resistor that highlights the excellent features in tunability with more than 200Hz of tuning range for the resonance frequency and an occupied area of merely 0.021mm2. This filter has been designed to provide a resonance frequency of 375Hz and a quality factor of 5. The OTAs have been biased in sub-threshold region, exhibiting an overall power consumption of 176nW with a supply voltage of 0.8V. An improved implementation of the Switched-Resistor filter has been proposed based on the distribution of the polysilicon resistor. The proposed Distributed Switched-Resistor (DSR) approach aims to strongly mitigate the effect of parasitic capacitances on the value of the equivalent resistance even when exploiting very small values for the duty cycle, thus allowing resistance multiplication factors up to a few thousands. For this purpose, the design of an 8th-order filter obtained through the cascade of four DSR biquadratic filters has been proposed for the deep brain stimulation application. Measured results on a biquadratic filter show excellent performance in tunability, both for the resonance frequency, which can be tuned from 13Hz to 517Hz, and the quality factor, which ranges from 1.6 up to 13. The measurement results have been carried out with a supply voltage of 0.5 V, providing an overall power consumption of merely 110nW. Subsequently, an important building-block circuit as the Transimpedance amplifier (TIA) has been presented for biomedical applications. The proposed TIA exploits for the first time in the literature a Switched–Resistor as the feedback element in order to achieve a digitally tunable transimpedance gain with an extremely large tuning range (higher than 80 dB) and a maximum value as high as 10 GΩ. Simulation results have shown a minimum IRCSN (input-referred current spectrum noise) of 1.67 fA/√Hz and a total power consumption of 0.9 μW with a 0.6 V supply voltage. Extensive parametric and Monte Carlo simulations have confirmed excellent robustness against PVT and mismatch variations. The dissertation entails the design of some neural front-ends. For this purpose, a LNA-shared architecture has been proposed that exploits a wide-band LNA in a frequency-division multiplexing mode. This work aims to provide design rules to deal with trade-offs between input-referred noise, bandwidth, and power consumption, analysing the main CMOS structures to enhance the overall performance of a generic neural front-end. Furthermore, an innovative high-density architecture has been proposed that exploits a double switching approach. At the system level, the time-division multiplexing mode allows for increasing the number of electrodes processed by the neural front-end and rejecting the EDO at the same time. The open-loop chopper-stabilization neural front-end has been fabricated in a 0.13μm CMOS process with an occupied area of 0.0268mm2, consuming about 2μA from a 0.8V supply voltage. It achieves an integral noise of 4.19μVrms (2.58μVrms) from 1 to 10kHz (from 300 to 7.5kHz) and results in a noise efficiency factor (NEF) of 2.17 (1.62). Besides achieving a maximum gain of 38.67dB with a tuning range of about 12dB. In the framework of a research cooperation with Corticale S.R.L., a Time-Interleaved ADC-SAR has been developed and an experimental prototype has been realized. The proposed 12-bit Time-Interleaved ADC-SAR aims to convert 256 signals from a shank-based SiNPAS probe. The proposed design has been realized in a 180nm CMOS technology (1P6M) with a supply voltage of 1.8V, guaranteeing a sampling frequency of 6.667MHz with a reference clock frequency of 100MHz. The preliminary measurement results have shown an ENOB of 11.6 bits with a noise floor below the LSB, equal to 256μV_RMS, showing an occupied area of 0.229mm2.